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Features
* * * * * * * * * * * * *
3.0V to 5.5V Operating Range Advanced Low Voltage, Zero Power, Electrically Erasable Programmable Logic Device Edge-Sensing "Zero" Power Low Voltage Equivalent of ATF22V10CZ "Zero" Standby Power (25 A Maximum) Ideal for Battery Powered Systems 25 ns Maximum Propagation Delay CMOS and TTL Compatible Inputs and Outputs Latch Feature Hold Inputs to Previous Logic States Advanced E2 Technology Reprogrammable 100% Tested High Reliability CMOS Process 20 Year Data Retention 100 Erase/Write Cycles 2,000V ESD Protection 200 mA Latchup Immunity Commercial and Industrial Temperature Ranges Dual-in-Line and Surface Mount Standard Pinouts
High Performance E2 PLD ATF22LV10CZ
Block Diagram
Pin Configurations
Pin Name CLK IN I/O VCC Function Clock Logic Inputs Bidirectional Buffers (3 to 5.5V) Supply
CLK/IN IN IN IN IN IN IN IN IN IN IN GND 1 2 3 4 5 6 7 8 9 10 11 12
TSSOP Top View
24 23 22 21 20 19 18 17 16 15 14 13 VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IN
ATF22LV10CZ
DIP/SOIC
PLCC
Top view
Note: For PLCC, pins 1, 8, 15, and 22 can be left unconnected. For superior performance, connect VCC to pin 1 and GND to pins 8, 15, and 22.
Rev. 0779E/LV10CZ-E-05/98
Description
The ATF22LV10CZ is a high performance CMOS (Electrically Erasable) Programmable Logic Device (PLD) which utilizes Atmel's proven electrically erasable Flash memory technology and provides 25 ns speed with stand-by current of 25 A maximum. All speed ranges are specified over the 3.0V to 5.5V range for industrial and commercial temperature ranges. The ATF22LV10CZ provides a low voltage and edgesensing "zero" power CMOS PLD solution with "zero" standby power (5 A typical). The ATF22LV10CZ powers down automatically to the zero power mode through Atmel's patented Input Transition Detection (ITD) circuitry when the device is idle. The ATF22LV10CZ is capable of operating at supply voltages down to 3.0V. Pin "keeper" circuits on input and output pins hold pins to their previous logic levels when idle, which eliminate static power consumed by pull-up resistors. The ATF22LV10CZ macrocell incorporates a variable product term architecture. Each output is allocated from 8 to 16 product terms which allows highly complex logic functions to be realized. Two additional product terms are included to provide synchronous reset and asynchronous reset. These additional product terms are common to all 10 registers and are automatically cleared upon power up. Register Preload simplifies testing. A Security Fuse prevents unauthorized copying of programmed fuse patterns.
Absolute Maximum Ratings*
Temperature Under Bias................... -40C to +85C Storage Temperature...................... -65C to +150C Voltage on Any Pin with Respect to Ground......................... -2.0V to +7.0V (1) Voltage on Input Pins with Respect to Ground During Programming.................... -2.0V to +14.0V (1) Programming Voltage with Respect to Ground....................... -2.0V to +14.0V (1)
*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Note:
1. Minimum voltage is -0.6V dc, which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is Vcc + 0.75V dc, which may overshoot to 7.0V for pulses of less than 20 ns.
DC and AC Operating Conditions
Commercial Operating Temperature (Case) VCC Power Supply 0C - 70C 3.0V - 5.5V Industrial -40C - 85C 3.0V - 5.5V
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ATF22LV10CZ
ATF22LV10CZ
Functional Logic Diagram Description
The Functional Logic Diagram describes the ATF22LV10CZ architecture. The ATF22LV10CZ has 12 inputs and 10 I/O macrocells. Each macrocell can be configured into one of four output configurations: active-high/low or registered/combinatorial. The universal architecture of the ATF22LV10CZ can be programmed to emulate most 24-pin PAL devices. Unused product terms are automatically disabled by the compiler to decrease power consumption. A Security Fuse, when programmed, protects the contents of the ATF22LV10CZ. Eight bytes (64 fuses) of User Signature are accessible to the user for purposes such as storing project name, part number, revision or date. The User Signature is accessible regardless of the state of the Security Fuse.
DC Characteristics
Symbol Parameter IIL IIH ICC ISB IOS (1) VIL VIH VOL Input or I/O Low Leakage Current Input or I/O High Leakage Current Clocked Power Supply Current Condition 0 VIN VIL(MAX) VCC - 0.7V VIN VCC VCC = MAX, Outputs Open, f = 15 MHz Com. Ind. Com. Ind. 55 60 5 5 Min Typ Max -10 10 85 90 25 50 -130 -0.5 2.0 VIN = VIH or VIL VCC = MIN, IOL = 8 mA VIN = VIH or VIL, VCC = MIN, IOH = -4.0 mA Com. Ind. 2.4 0.8 VCC + 0.75 0.5 Units A A mA mA A A mA V V V V
Power Supply Current, VCC = MAX, Standby VIN = MAX, Outputs Open Output Short Circuit Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VOUT = 0.5V
VOH
Note:
1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
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AC Waveforms
INPUTS, I/O REG. FEEDBACK SYNCH. PRESET
tS
tH tW tW
CP tP tAW ASYNCH. RESET tCO REGISTERED OUTPUTS tPD COMBINATORIAL OUTPUTS VALID VALID tAP VALID tER VALID tER tEA OUTPUT DISABLED tEA OUTPUT DISABLED VALID VALID tAR
AC Characteristics (1)
-25 Symbol tPD tCF tCO tS tH tP tW FMAX tEA tER tAP tSP tAW tAR tSPR
Note:
Parameter Input to Feedback to Non-Registered Output Clock to Feedback Clock to Output Input or Feedback Setup Time Input Hold Time Clock Period Clock Width External Feedback 1/(tS + tCO) Internal Feedback 1/(tS + tCF) No Feedback 1/(tP) Input to Output Enable Input to Output Disable Input or I/O to Asynchronous Reset of Register Setup Time, Synchronous Preset Asynchronous Reset Width Asynchronous Reset Recovery Time Synchronous Preset to Clock Recovery Time
Min
Max
Units ns ns ns ns ns ns ns MHz MHz MHz
3 2 15 0 25 12.5 33.3 35.7 40.0 3 3 3 15 25 25 15
25 13 15
25 25 25
ns ns ns ns ns ns ns
1. See ordering information for valid part numbers.
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ATF22LV10CZ
ATF22LV10CZ
Input Test Waveforms and Measurement Levels
Output Test Loads
Note: Similar competitors' devices are specified with slightly different loads. These load differences may affect output signals' delay and slew rate. Atmel devices are tested with sufficient margins to meet compatible device specification conditions.
Pin Capacitance (f = 1 MHz, T = 25C) (1)
Typ CIN COUT
Note:
Max 8 8
Units pF pF
Conditions VIN = 0V VOUT = 0V
5 6
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
5
Power Up Reset
The registers in the ATF22LV10CZ are designed to reset during power up. At a point delayed slightly from VCC crossing VRST, all registers will be reset to the low state. The output state will depend on the polarity of the buffer. This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the uncertainty of how VCC actually rises in the system, the following conditions are required: 1. The VCC rise must be monotonic and start below 0.7V 3. The clock must remain stable during TPR. 2. After TPR, all input and feedback setup times must be met before driving the clock pin high.
Electronic Signature Word
There are 64 bits of programmable memory that are always available to the user, even if the device is secured. These bits can be used for user-specific data.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying of the ATF22LV10CZ fuse patterns. Once programmed, fuse verify and preload are inhibited. However, the 64-bit User Signature remains accessible. The security fuse should be programmed last, as its effect is immediate.
Programming/Erasing Preload of Register Outputs
The ATF22LV10CZ's registers are provided with circuitry to allow loading of each register with either a high or a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A JEDEC file with preload is generated when a source file with vectors is compiled. Once downloaded, the JEDEC file preload sequence will be done automatically by most of the approved programmers after the programming. Parameter TPR VRST Description Power-Up Reset Time Power-Up Reset Voltage Typ 600 2.3 Programming/erasing is performed using standard PLD programmers. See CMOS PLD Programming Hardware & Software Support for information on software/programming.
Max 1,000 2.7
Units ns V
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ATF22LV10CZ
ATF22LV10CZ
Input and I/O Pin Keepers
All ATF22LV10CZ family members have internal input and I/O pin-keeper circuits. Therefore, whenever inputs or I/Os are not being driven externally, they will maintain their last driven state. This ensures that all logic array inputs and device outputs are at known states. These are relatively weak active circuits that can be easily overridden by TTL-compatible drivers (see input and I/O diagrams below).
Input Diagram
I/O Diagram
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Functional Logic Diagram ATF22LV10CZ
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ATF22LV10CZ
ATF22LV10CZ
tPD (ns) 25 tS (ns) 15 tCO (ns) 15 Ordering Code ATF22LV10CZ-25JC ATF22LV10CZ-25PC ATF22LV10CZ-25SC ATF22LV10CZ-25XC ATF22LV10CZ-25JI ATF22LV10CZ-25PI ATF22LV10CZ-25SI ATF22LV10CZ-25XI Package 28J 24P3 24S 24X 28J 24P3 24S 24X Operation Range Commercial (0C to 70C)
15
15
Industrial (-40C to +85C)
Package Type
28J 24P3 24S 24X
28-Lead, Plastic J-Leaded Chip Carrier (PLCC) 24-Lead, 0.300" Wide, Plastic Dual Inline Package (DIP) 24-Lead, 0.300" Wide, Plastic Gull WIng Small Outline (SOIC) 24-Lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP)
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